1. Field of the Invention
The invention relates to data output buffers for use in semiconductor memory system, and more particularly, to data output buffers implements a junction field effect transistor (hereinafter referred to as a JFET).
2. Description of the Prior Art
An output end of a semiconductor memory system employs a data output buffer in order to provide a TTL logic level. A conventional data output buffer uses a logic circuit for receiving output data from a memory cell via a sense amplifier and receives an output enable clock pulse for controlling the output. A N-channel pull-down MOSFET transistor has a drain connected to an output terminal.
In the data output buffer, when input data at the output terminal from a sensor amplifier is low and the output enable clock pulse is low, the output terminal has a high impedance, thereby isolating the semiconductor memory from circuitry connected to the output terminal to receive output data. A low level input and low level input enables transistors to conduct, thereby providing a logic low level for output. Due to certain timing features however, data of a high level may exist before the pull-down transistor is turned on, and a voltage level of invalid data at this time increases with the higher power supply voltage V.sub.cc. Therefore, in the case that invalid data is at a high level and valid data is at a low level of the power supply voltage V.sub.cc, a high VGS and VDS of the pull-down transistor causes a very high maximum value of current in the pull-down transistor and subsequently organization of V.sub.ss noise, and as result, variation of the output level and adverse operation of the circuitry connected to the output terminal It is desirable to minimize the channel width of a pull-down transistor coupled between the output terminal and V.sub.ss in order to prevent such V.sub.ss noise. Minimizing the channel width of transistor TN2, however, is concerned with the problem that an excess time is longer when the power supply voltage is at the low level, due to longer response time. Furthermore, the TTL low level output value at the output terminal is higher than zero level due to the higher voltage of the output data Do resulting from the greater turn-on resistance of the pull-down transistor.
In one draft to address such deficiencies, a permanent resistor is connected between the power supply voltage V.sub.cc and the source of a transistor interposed between V.sub.cc and the pull-down transistor in order to minimize noise when the output data is lowered. The application of such a resistor enables the V.sub.ss noise to be minimized by delaying the gating of the pull-down transistor, but delays the data excess time with almost all of the power supply voltage is unavoidable because the resistor holds a constant value; however, the value of the power supply voltage is variable. Therefore, there is a problem that the operational speed is delayed when the power supply voltage is at the low level.